Embodiments of the present invention relates to a nonvolatile memory device and a method for controlling the same, and more specifically, to a technology capable of reducing a cell operation time in a memory device performing a program operation and a data sensing operation.
Memory devices may be classified into volatile and nonvolatile memory devices. The nonvolatile memory devices use nonvolatile memory cells which can retain stored data even when power is interrupted. Examples of the nonvolatile memory devices include flash random access memory (RAM) and phase change RAM (PRAM).
The PRAM includes memory cells that are implemented using a phase change material (PCM), e.g., germanium antimony tellurium (GST). If heat is applied to the GST, the GST changes to a crystalline phase or an amorphous phase to store data in the memory cells.
Nonvolatile memory devices such as a magnetic memory and a PRAM have a data processing speed as high as volatile RAMs, and can retain data even when power is interrupted.
FIGS. 1A and 1B are diagrams showing a conventional phase change resistor (PCR) element 4.
The PCR element 4 includes a top electrode 1, a bottom electrode 3, and a phase change material (PCM) layer 2 interposed therebetween. When a voltage and a current are applied to the PCR element 4, a high temperature is induced in the PCM layer 2 and thus an electrical conduction state of the PCM layer 2 changes depending on resistance variation.
AgInSbTe is usually used as a material for the PCM layer 2. The PCM layer 2 uses a chalcogenide which includes chalcogen elements, e.g., S, Se and Te as main components. Specifically, the PCM layer 2 uses a germanium antimony tellurium alloy (Ge2Sb2Te5) composed of Ge—Sb—Te.
FIGS. 2A and 2B are diagrams showing a phase changing principle of the conventional PCR element 4.
As illustrated in FIG. 2A, if a low current smaller than a threshold value flows through the PCR element 4, the temperature of the PCR element 4 becomes suitable for crystallization of the PCM layer 2. Accordingly, the PCM layer 2 changes to a crystalline phase and thus goes to a low resistance state.
On the other hand, as illustrated in FIG. 2B, if a high current larger than the threshold value flows through the PCR element 4, the temperature of the PCM layer 2 rises above the melting point. Accordingly, the PCM layer 2 changes to an amorphous phase and thus goes to a high resistance state.
As such, the PCR element 4 can store data corresponding to two resistance states in a nonvolatile manner. That is, assuming that the PCM element 4 is in the low resistance state corresponds to data “1” and a case in which the PCM element 4 is in the high resistance state corresponds to data “0”, two logic states of data can be stored in the PCR element 4.
FIG. 3 is a diagram showing a write operation of a conventional PCR cell.
High heat is generated when a current flows between the top electrode 1 and the bottom electrode 3 of the PCR element 4 for a predetermined time. Accordingly, the PCM layer 2 changes to the crystalline phase or the amorphous phase, depending on the temperature applied to the top electrode 1 and the bottom electrode 3.
When a low current flows for a predetermined time, the PCM layer 2 has the crystalline phase formed by a low-temperature heating state thereof, and the PCR element 4 becomes a low resistance element having a set phase. On the other hand, when a high current flows for a predetermined time, the PCM layer 2 has the amorphous phase formed by a high-temperature heating state thereof, and the PCR element 4 becomes a high resistance element having a reset phase. Therefore, the difference of the two phases is exhibited as electrical resistance variation.
Accordingly, in order to write the set phase in the write operation, a low voltage is applied to the PCR element 4 for a long time. On the other hand, in order to write the reset phase in the write operation, a high voltage is applied to the PCR element 4 for a short time.
FIG. 4 is a configuration diagram of a conventional PRAM.
The conventional PRAM includes a cell array 10, a switching unit 11, a precharge unit 12, a write driving unit 13, a clamping unit 14, a precharge unit 15, a current-to-voltage conversion unit 16, and a sense amplifier 17.
The cell array 10 includes a plurality of phase change memory cells each of which has a PCR element. Each memory cell includes a variable resistor element and an access element. The variable resistor element has a phase change material having one of two different resistances depending on a crystalline phase or an amorphous phase. The access element controls a current flowing through the variable resistor element.
A ground voltage GND or a pumping voltage VPP is applied to the cell array 10 through a word line WL.
The switching unit 11 selects a column of a phase change memory cell in the cell array 10 where data is to be written or read out.
The precharge unit 12 precharges an input/output line SIO with a peripheral voltage VPERI in response to a precharge signal PCG1 before a data sensing operation.
The write driving unit 13 controls a program operation by supplying the input/output line SIO with a write voltage corresponding to data to be written.
The clamping unit 14 clamps a voltage level of the input/output line SIO to a voltage range suitable for a read operation in response to a clamp signal CMP.
The precharge unit 15 precharges a sensing line SAI with a voltage VSA in response to a precharge signal PCG2 during the data sensing operation.
The current-to-voltage conversion unit 16 converts a current flowing through the sensing line SAI into a voltage in response to a sensing control signal SAIL. The sensing control signal SAIL corresponds to a constant current source. A bias voltage of the sensing control signal SAIL is applied with a level at which a phase of a phase change material (GST) is changed. In this case, when the GST has a set phase, a current level of the sensing line SAI is lowered.
The sense amplifier 17 is coupled to the sensing line SAI, and senses and amplifies a voltage of the sensing line SAI according to a read reference voltage VRDref.
FIG. 5 is a waveform diagram showing the program operation and the read operation on the PRAM in FIG. 4.
When a program signal PGM is applied in a write operation mode, a high voltage is applied to the PCR element for a short time in order to write the reset data. After the program operation is completed, a precharge operation is performed. Subsequently, when a read signal RD is applied, a read current is applied, and a read operation on the reset data is performed.
On the other hand, when the program signal PGM is applied in the write operation mode, a low voltage is applied to the PCR element for a long time in order to write the set data. After the program operation is completed, the precharge operation is performed. Subsequently, when the read signal RD is applied, a read current is applied and a read operation on the set data is performed.
The conventional PRAM requires different functions in order to perform the program operation and the data sensing operation.
That is, the program operation is performed through the write driving unit 13, and the precharge operation is performed through the precharge units 12 and 15. Then, the read operation is performed using the clamping unit 14, the current-to-voltage conversion unit 16, and the sense amplifier 17.
In this case, a separate circuit for performing the program operation and for performing the data sensing operation must be provided. Therefore, a cell data program time and data sensing time becomes longer, and a layout area increases.